Senior Chip Design Verification Engineer
Location:
Chennai / Sunnyvale
Experience Required:
3+ Years
Job Description:
We are looking for Senior Design Verification Engineers with strong hands-on expertise in SystemVerilog, UVM and high-speed protocol verification.
Key Responsibilities:
● Perform functional verification at block and chip level for ASIC/SoC designs.
● Build UVM-based testbenches from scratch for new IPs or subsystems.
● Develop and execute detailed verification test plans based on design specifications.
● Write directed and constrained-random test cases; debug simulation failures.
● Perform coverage analysis (functional and code) and drive closure.
● Work with RAL (Register Abstraction Layer) to verify register-level functionality.
● Develop and validate assertions for protocol and functional correctness.
● Collaborate closely with RTL teams to ensure alignment across design phases.
● Work closely with RTL designers and architects to identify and resolve functional issues.
● Lead technical reviews, mentor and guide junior engineers in best practices, methodologies, and tools.
Required Qualifications:
● Bachelor's/Master's degree in Electrical/Electronics Engineering, Computer Science, or related field.
● 6+ years of hands-on ASIC/SoC Design Verification experience, preferably with tape-out exposure.
● Strong expertise in SystemVerilog and UVM.
● Hands-on experience with high-speed protocol verification.
Why Join us?
● Opportunity to work on cutting-edge chip designs for innovative products.
● Work with a dynamic and skilled team of engineers.
● Competitive salary and benefits package.
● Career growth opportunities in a fast-evolving field.
Our locations
INDIA
Edveon Technologies Pvt Ltd
1/3A 3B, Siruseri Natham Link Road,
Siruseri, Chennai, Tamil Nadu, 600130
USA
Edveon Inc
440 N Wolfe Rd, Cube E040
Sunnyvale, CA 94085